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W65C21S Peripheral Interface Adapter (PIA)
W65C21S Die

      W65C22S Die

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IP Data Deliverables

WDC provides the following Data Deliverables in our technology transfer.

Hard Core
GDSII Mask Files
GDSII Schematic Files N/A
GDSII Hard Core Flowchart N/A
Spice Extracted Netlist
CDL Netlist for LVS
Mask ROM files  N/A
Verilog Structural Gate Netlist N/A
Viewlogic Files
Viewlogic Standard Product Behavioral Model Footprint NP
Viewlogic Behavioral Core Footprint NP
Viewlogic Standard Product Gate Model Footprint NP
Viewlogic Buffer Ring NP
Viewlogic Gate Core Footprint NP
Soft Core
Verilog RTL Model NP
Firm Core
Xilinx Synthesized Gate Model NP
Common Files
Verilog Test files N/A
Sentry Test files

N/A – Not Applicable
NP – Not Planned
UC – Under Construction

WDC's microprocessor IP has been tailored for ease of reuse. The hard core IP is in the industry standard GDSII format.The buffer ring has been designed with off-chip drivers, including latch-up and ESD protection. When the core is embedded,the off-chip buffer ring is replaced with On-Chip-Bus (OCB) interface ring. The abstract cell is the connecting points with labels that provide core verification and system verification. WDC's test programs require that all test pins be compared to the standard test vendors.


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2166 E. Brown Rd. Mesa, Arizona 85213
phone: 480 962-4545, fax: 480 835-6442

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Last updated 10/11/2016
Current date 12.16.2018
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