W65C22S Versatile Interface Adapter (VIA)

W65C22S Die

Quick Links Cores Page Sample (RFS) W65C22S Datasheet Design Kits Development Tools Chip Applications Core Applications

WDC provides the following Data Deliverables in our technology transfer.

	Hard Core
	GDSII Mask Files GDSII Schematic Files GDSII Hard Core Flowchart N/A Spice Extracted Netlist CDL Netlist for LVS Mask ROM files  N/A Verilog Structural Gate Netlist
	Viewlogic Files
	Viewlogic Standard Product Behavioral Model Footprint NP Viewlogic Behavioral Core Footprint NP Viewlogic Standard Product Gate Model Footprint Viewlogic Buffer Ring Viewlogic Gate Core Footprint
	Soft Core
	Verilog RTL Model NP
	Firm Core
	Xilinx Synthesized Gate Model NP
	Common Files
	Verilog Test files Sentry Test files

N/A ­ Not Applicable
NP ­ Not Planned
UC ­ Under Construction

WDC's microprocessor IP has been tailored for ease of reuse. The hard core IP is in the industry standard GDSII format.The buffer ring has been designed with off-chip drivers, including latch-up and ESD protection. When the core is embedded,the off­chip buffer ring is replaced with On­Chip­Bus (OCB) interface ring. The abstract cell is the connecting points with labels that provide core verification and system verification. WDC's test programs require that all test pins be compared to the standard test vendors.